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CYRS1543AV18 cyrs1545av18 72-mbit qdr ? ii+ sram four-word burst architecture with radstop? technology cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-60007 rev. *h revised january 4, 2013 72-mbit qdr ? ii+ sram four-word burst architecture with radstop? technology radiation performance radiation data total dose = ? 300 krad soft error rate (both heavy ion and proton) heavy ions ?? 1 10 -10 upsets/bit-day with single error correction - double error detection error detection and correction (sec-ded edac) neutron s = 2.0 10 14 n/cm 2 dose rate = 2.0 10 9 rad(si)/sec dose rate survivability (rad(si)/ sec) = 1.5 10^11 (rad(si)/sec latch up immunity = 120 mev.cm 2 /mg (125 c) prototyping non-qualified cypt1543av18, and cypt1545av18 devices with same functional and timing characteristics in a 165-ball ceramic column grid array (ccga) package features separate independent read and write data ports ? supports concurrent transactions 250 mhz clock for high bandwidth 4-word burst for reducing address bus frequency double data rate (ddr) interfaces on both read and write ports at 250 mhz (data transferred at 500 mhz) two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data capture in high speed systems single multiplexed address input bus latches address inputs for read and write ports separate port selects for depth expansion synchronous internally self-timed writes qdr ? ii+ operates with 2.0 cycle read latency when the delay lock loop (dll) is enabled available in 18, and 36 configurations full data coherency, providing most current data core v dd = 1.8 ( 0.1 v); i/o v ddq = 1.4 v to v dd available in 165-ball ccga (21 25 2.83 mm) hstl inputs and variable drive hstl output buffers jtag 1149.1 compatible test access port dll for accurate data placement configurations CYRS1543AV18 ? 4 m 18 cyrs1545av18 ? 2 m 36 functional description the CYRS1543AV18 and cyrs1545av18 are synchronous pipelined srams, equipped with 1. 8 v qdr ii+ architecture with radstop? technology. cypress?s state-of-the-art radstop technology is radiation hardened through proprietary design and process hardening techniques. the qdr ii+ architecture consists of two separate ports: the read port and the write port to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. qdr ii+ architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that exists with common i/o device s. each port can be accessed through a common address bus. addresses for read and write addresses are latched on alternat e rising edges of the input (k) clock. accesses to the qdr ii+ read and write ports are completely independent of one another. to maximize data throughput, both read and write ports are equipped with ddr interfaces. each address location is associated with four 18-bit words (CYRS1543AV18) or 36-bit words (cyrs1545av18) that burst sequentially into or out of the device. because data can be transferred into and out of the device on every rising edge of both input clocks (k and k ), memory bandwidth is maximized while simplifying system design by el iminating bus turnarounds. depth expansion is accomplished with port selects, which enables each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the k or k input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide description 250 mhz unit maximum operating frequency 250 mhz maximum operating current (125c, concurrent r/w) 18 1225 ma 36 1225
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 2 of 32 logic block diagram ? CYRS1543AV18 1m x 18 array clk a (19:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 36 20 72 18 bws [1:0] v ref write add. decode write reg 36 a (19:0) 20 1m x 18 array 1m x 18 array 1m x 18 array 18 cq cq doff q [17:0] 18 qvld 18 18 18 write reg write reg write reg logic block diagram ? cyrs1545av18 512 k x 36 array clk a (18:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps control logic address register reg. reg. reg. 72 19 144 36 bws [3:0] v ref write add. decode write reg 72 a (18:0) 19 512 k x 36 array 512 k x 36 array 512 k x 36 array 36 cq cq doff q [35:0] 36 qvld 36 36 36 write reg write reg write reg
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 3 of 32 contents manufacturing flow .......................................................... 4 radiation hardened design ...... .............. ........... ......... 4 neutron soft error immunity ........................................... 4 pin configuration ............................................................. 5 pin definitions .................................................................. 6 functional overview ........................................................ 8 read operations ......................................................... 8 write operations ......................................................... 8 byte write operations ................................................. 8 concurrent transactions ..... ........................................ 8 depth expansion ......................................................... 9 programmable impedance ........ .............. ........... ......... 9 echo clocks .......... .............. .............. .............. ............ 9 valid data indicator (qvld) ........................................ 9 dll .............................................................................. 9 qualification and screening ........................................ 9 application example ...................................................... 10 truth table ...................................................................... 11 write cycle descriptions ............................................... 11 write cycle descriptions ............................................... 12 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 13 disabling the jtag feature ...................................... 13 test access port ....................................................... 13 performing a tap re set ........................................... 13 tap registers ........................................................... 13 tap instruction set ................................................... 13 tap controller state diagram ....................................... 15 tap controller block diagram ...................................... 16 tap electrical characteristics ...................................... 16 tap ac switching characteristics ............................... 17 tap timing and test conditions .................................. 18 identification register definitions ................................ 19 scan register sizes ....................................................... 19 instruction codes ........................................................... 19 boundary scan order .................................................... 20 power up sequence in qdr ii+ sram ......................... 21 power up sequence ................................................. 21 dll constraints ......................................................... 21 maximum ratings ........................................................... 22 operating range ............................................................. 22 electrical characteristics ............................................... 22 dc electrical characteristics ..................................... 22 ac electrical characteristics ..................................... 23 radiation performance .................................................. 23 capacitance .................................................................... 23 thermal resistance ........................................................ 23 ac test loads and waveforms ..................................... 24 switching characteristics .............................................. 25 switching waveforms .................................................... 26 ordering information ...................................................... 27 ordering code definitions ..... .................................... 27 package diagram ............................................................ 28 acronyms ........................................................................ 29 document conventions ................................................. 29 units of measure ....................................................... 29 glossary .......................................................................... 30 document history page ................................................. 31 sales, solutions, and legal information ...................... 32 worldwide sales and design s upport ......... .............. 32 products .................................................................... 32 psoc solutions ......................................................... 32
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 4 of 32 radiation hardened design the single event latch up (sel) immunity is improved by a radiation hardened design technique developed by cypress called radstop. this design mitigation technique allows the sel performance to achieve radiation hard performance levels. manufacturing flow step screen method requirement 1 wafer lot acceptance test tm 5007 2 internal visual 2010, condition a 100% 3 serialization 100% 4 temperature cycling 1010, condition c, 50 cycles minimum 100% 5 constant acceleration 2001, yi orientation only 100% 6 condition tbd (package in design) 7 particle impact noise detecti on (pind) 2020 condition a 100% 8 radiographic (x-ray) 2012, one view (y-1 orientation) only 9 pre burn in electrical parameters in accordance with applicable cypress specification 100% 10 dynamic burn in 1015, condition d 100% 240 hours at 125 c or 120 hours at 150 c minimum 11 interim (post dynamic burn in) electricals in accordance with applicable cypress device specifications 100% 12 static burn in 1015, condition c, 72 hou rs at 150 c or 144 hours at 125 c minimum 100% 13 interim (post static burn in) electricals in accordan ce with applicable cypress device specifications 100% 14 percentage defective allowable (pda) calculation 5% overall, 3% functional parameters at 25 c all lots 15 final electrical test in accordance with applicable cypress device specifications 100% a. static tests (1) 25 c 5005, table i, subgroup 1 (2) ?55 c and +125 c 5005, table i, subgroup 2, 3 b. functional tests (1) 25 ? c 5005, table i, subgroup 7 (2) ?55 c and +125 c 5005, table i, subgroup 8a, 8b c. switching test at 25 c 5005, table i, subgroup 9 16 seal (fine and gross leak test) 1014 100% 17 external visual 2009 100% 18 wafer lot specific life test (group c) mil-prf 38535 , appendix b, section b.4.2.c all wafer lots neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 320 368 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. for more details refer to application note an54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates?
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 5 of 32 pin configuration pin configurations for CYRS1543AV18 and cyrs1545av18. [1] figure 1. 165-ball ccga pinout CYRS1543AV18 (4 m 18) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/144m a wps bws 1 k nc/288m rps aacq b nc q9 d9 a nc k bws 0 ancncq8 c nc nc d10 v ss ancav ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss aaav ss nc nc d1 p nc nc q17 a a qvld a a nc d0 q0 r tdotckaaancaaatmstdi cyrs1545av18 (2 m 36) 1 2 3 4 5 6 7 8 9 10 11 a cq nc/288m a wps bws 2 k bws 1 rps a nc/144m cq b q27 q18 d18 a bws 3 kbws 0 ad17q17q8 c d27 q28 d19 v ss ancav ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss aaav ss q10 d9 d1 p q35 d35 q26 a a qvld a a q9 d0 q0 r tdotckaaancaaatmstdi note 1. nc/144m and nc/288m are not connected to the die and can be tied to any voltage level.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 6 of 32 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals . sampled on the rising edge of k and k clocks when valid write operations are active. CYRS1543AV18 ? d [17:0] cyrs1545av18 ? d [35:0] wps input- synchronous write port select ? active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initiated. deasserting deselects the write port. deselecting the write port ignores d [x:0] . bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select (bws) 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks when write operations are active. used to select which byte is wri tten into the device during the current portion of the write operations. by tes not written remain unaltered. CYRS1543AV18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cyrs1545av18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the bws are sampled on the same edge as the data. deselecting a bws ignores the corresponding byte of data and it is not written into the device . a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 4 m 18 (4 arrays each of 1 m 18) for CYRS1543AV18 and 2 m 36 (4 arrays each of 512 k 36) for cyrs1545av18. therefore, only 20 address inputs for CYRS1543AV18 and 19 address inputs for cyrs1545av18. these inputs are igno red when the appropriate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the requested data when the read operation is active. valid data is driven out on the rising edge of the k and k clocks during read operations. on deselecting the read port, q [x:0] are automatically tristated. CYRS1543AV18 ? q [17:0] cyrs1545av18 ? q [35:0] rps input- synchronous read port select ? active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting deselect s the read port. when deselected, the pending access is allowed to complete and the output drivers are au tomatically tristated followi ng the next rising edge of the k clock. each read access consists of a burst of four sequential transfers. qvld valid output indicator valid output indicator . the q valid indicates valid output data. qvld is edge aligned with cq and cq . k input clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. cq echo clock cq referenced wi th respect to c . this is a free running clock and is synchronized to the input clock k. the timings for the echo clocks are shown in the switching characteristics on page 25 . cq echo clock cq referenced with respect to c . this is a free running clock and is synchronized to the input clock k . the timings for the echo clocks are shown in the switching characteristics on page 25 . zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 rq, where rq is a resistor connected between zq and ground. alternatively, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin ca nnot be connected directly to gnd or left unconnected. doff input dll turn off ? active low . connecting this pin to ground turns off the dll inside the device. the timings in the dll turned off operation differs from t hose listed in this data sheet. for normal operation, this pin can be connected to a pull up through a 10 k ? or less pull up resistor. the device behaves in qdr i mode when the dll is turned off. in this mode, the device can be operated at a frequency of up to 167 mhz with qdr i timing. tdo output test data out (tdo) for jtag .
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 7 of 32 tck input test clock (tck) pin for jtag . tdi input test data in (tdi) pin for jtag . tms input test mode select (tms) pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs, outputs, and ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 8 of 32 functional overview the CYRS1543AV18, cyrs1545av18 are synchronous pipelined burst srams with a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and flows out th rough the read port. these devices multiplex the address inputs to minimize the number of address pins required. by having sepa rate read and write ports, the qdr ii completely eliminates the need to turnaround the data bus and avoids any possible dat a contention, th ereby simplifying system design. each access consists of four 18-bit data transfers in the case of CYRS1543AV18, and four 36-bit data transfers in the case of cyrs1545av18 in two clock cycles. this device operates with a re ad latency of two cycles when doff pin is tied high. when doff pin is set low or connected to v ss then device behaves in qdr i mode with a read latency of one clock cycle. accesses for both ports are initiated on the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the output clocks (k and k ). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the output clocks (k and k ). all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). CYRS1543AV18 is described below. the same basic descriptions also apply to cyrs1545av18. read operations the CYRS1543AV18 is organized internally as four arrays of 1 m 18. accesses are completed in a burst of four sequential 18-bit data words. read operat ions are initiated by asserting rps active at the rising edge of the positive input clock (k). the address presented to the address inputs is stored in the read address register. following the next two k clock rise, the corresponding lowest order 18-bit word of data is driven onto the q [17:0] using k as the output timing reference. on the subsequent rising edge of kb, the next 18-bit data word is drive onto the qq [17:0] . this process continues until all four 18-bit data words have been driven out onto q [17:0] . the requested data is valid 0.45 ns from the rising edge of the output clock (k or k ). to maintain the internal logic, each read access must be allowed to complete. each read access consists of four 18-bit data words and takes two clock cycles to complete. therefore, read accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device ignores the second read request. read accesses can be initiated on every other k clock rise. doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks (k and k ). when the read port is deselec ted, the CYRS1543AV18 first completes the pending read transactions. synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the positive input clock (k). this allows for a seamless transition between device s without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting wps active at the rising edge of the positive input clock (k). on the following k clock rise the data presented to d [17:0] is latched and stored into the lower 18-bit write data register, provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register, provided bws [1:0] are both asserted active. this process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the sram. the 72 bits of data are then written into the memory array at the specified location. therefore, write accesses to the device can not be initiated on two consecutive k clock rises. the internal logic of the device ignores the second write request. write accesses can be initiated on every other rising edge of the positive input clock (k). doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the in put clocks (k and k ). when deselected, the write port ignores all inputs after the pending write operations have been completed. byte write operations byte write operations are sup ported by the CYRS1543AV18. a write operation is initiated as described in the write operations section. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate bws i nput during the data portion of a write latches the data being presented and writes it into the device. deasserting the bws input during the data portion of a write allows the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read, modify, or write operations to a byte write operation. concurrent transactions the read and write ports on the CYRS1543AV18 operate independently of one another. as each port latches the address inputs on different clock edges, you can read or write to any location, regardless of the transaction on the other port. if the ports access the same location when a read follows a write in successive clock cycles, the sr am delivers the most recent information associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. read access and write access must be scheduled such that one transaction is initia ted on any clock cycle. if both ports are selected on the same k clock rise, the arbitration depends on the previous state of the sram. if both ports are deselected, the read port takes priority. if a read was initiated on the previous cycle, the write port ta kes priority (as read operations can not be initiated on consecutive cycles). if a write was initiated on the previous cycle, the read port takes priority (as write operations can not be initia ted on consecutive cycles). therefore, asserting both port selects active from a de selected state results in alter- nating read or write operations being initiated, with the first access being a read.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 9 of 32 depth expansion the CYRS1543AV18 has a port select input for each port. this allows for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the specified port. deselecting a port does not affect the other port. all pending transactions (read and write) are completed before the device is deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the value of rq must be 5 the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq =1.5 v. the output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the qdr ii+ to simplify data capture on high-speed systems. two echo clocks are generated by the qdr ii+. cq is referenced with respect to k and cq is referenced with respect to k . these are free-running clocks and are synchronized to the input clock of the qdr ii+. the timing for the echo clocks is shown in the switching characteristics on page 25 . valid data indicator (qvld) qvld is provided on the qdr ii+ to simplify data capture on high speed systems. the qvld is ge nerated by the qdr ii+ device along with data output. this signal is also edge-aligned with the echo clock and follows the timing of any data pin. this signal is asserted half a cycle befo re valid data arrives. dll these chips use a dll that is designed to function between 120 mhz and the specified maximum clock frequency. during power up, when the doff is tied high, the dll is locked after 10240 cycles of stable clock. the dll can also be reset by slowing or stopping the input clocks k and k for a minimum of 30 ns. the dll may be disabled by applying ground to the doff pin. when the dll is turned off, the device behaves in qdr i mode (with one cycle latency and a longer access time). for information refer to the application note an5062, dll consider- ations in qdrii/ddrii . qualification and screening the 90 nm radstop technology was qualified by cypress after meeting the criteria of the general manufacturing standards. the test flow includes screening units with the defined flow (class v) and the appropriate peri odic or lot conformance testing (groups b, c, d, and e). both the 90 nm process and the sram products are subject to period or lot based technology confor- mance inspection (tci) and quality conformance inspection (qci) tests, respectively. cypress offers both prototyping models and flight units of these product configurations. table 1. qualification tests group a general electrical tests group b mechanical - dimensions, bond strength, solvents, die shear, solderability, lead integrity, seal, and acceleration group c life tests - 1000 hours at 125 c or equivalent group d package related mechanical tests - shock, vibration, accel, salt, seal, lead finish adhesion, lid torque, thermal shock, and moisture resistance group e radiation tests
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 10 of 32 application example figure 2 shows four qdr ii+ used in an application. figure 2. application example bus master (cpu or asic) data in data out address source k source k vt vt vt r r d a k sram #2 rq = 250 ohms zq cq/cq q k rps wps bws d a k sram #1 cq/cq q k rps wps bws rps wps bws clkin1/clkin1 r = 50ohms, vt = v /2 ddq r rq = 250 ohms zq r clkin2/clkin2
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 11 of 32 truth table CYRS1543AV18 and cyrs1545av18 [2, 3, 4, 5, 6, 7] operation k rps wps dq dq dq dq write cycle: load address on the rising edge of k; input write data on two consecutive k and k rising edges. l?h h [8] l [9] d(a) at k(t + 1) ? d(a + 1) at k (t + 1) ? d(a + 2) at k(t + 2) ? d(a + 3) at k (t + 2) ? read cycle: (2.0 cycle latency) load address on the rising edge of k; wait two cycles; read data on two consecutive k and k rising edges. l?h l [9] x q(a) at k(t + 2) ? q(a + 1) at k (t + 2) ? q(a + 2) at k(t + 3) ? q(a + 3) at k (t + 3) ? nop: no operation l?h h h d = x q = high z d = x q = high z d = x q = high z d = x q = high z standby: clock stopped stopped x x previous state p revious state previous state previous state write cycle descriptions CYRS1543AV18 [2, 10] bws 0 bws 1 k k comments l l l?h ? during the data portion of a write sequence: CYRS1543AV18 ?? both bytes (d [17:0] ) are written into the device. l l ? l?h during the data portion of a write sequence ? CYRS1543AV18 ?? both bytes (d [17:0] ) are written into the device. l h l?h ? during the data portion of a write sequence: CYRS1543AV18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. l h ? l?h during the data portion of a write sequence ? CYRS1543AV18 ?? only the lower byte (d [8:0] ) is written into the device, d [17:9] remains unaltered. h l l?h ? during the data portion of a write sequence ? CYRS1543AV18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h l ? l?h during the data portion of a write sequence ? CYRS1543AV18 ?? only the upper byte (d [17:9] ) is written into the device, d [8:0] remains unaltered. h h l?h ? no data is written into the devices during this portion of a write operation. h h ? l?h no data is written into the devices during this portion of a write operation. notes 2. x = ?don't care,? h = logic high, l = logic low, ? represents rising edge. 3. device powers up deselected with the outputs in a tristate condition. 4. ?a? represents address location latched by the devices when trans action was initiated. a + 1, a + 2, and a +3 represents the address sequence in the burst. 5. ?t? represents the cycle at which a read/wr ite operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on k and k rising edges. 7. we recommend that k = k = high when clock is stopped. this is not essential, but permi ts most rapid restart by overcoming transmission line charging s ymmetrically. 8. if this signal was low to initiate the previous cycl e, this signal becomes a ?don?t care? for this operation. 9. this signal was high on previous k clock rise. initiating c onsecutive read or write operations on consecutive k clock rises i s not permitted. the device ignores the second read or write request. 10. is based on a write cycl e that was initiated in accordance with the write cycle descriptions table. bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 12 of 32 write cycle descriptions the write cycle description table for cyrs1545av18 follows. [11, 12] bws 0 bws 1 bws 2 bws 3 k k comments l l l l l?h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l?h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l?h ? during the data portion of a wr ite sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l?h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l?h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l?h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l?h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l?h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l?h ? during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l?h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h h l?h ? no data is written into the device during this portion of a write operation. h h h h ? l?h no data is written into the device during this portion of a write operation. notes 11. x = ?don't care,? h = logic high, l = logic low, ? represents rising edge. 12. is based on a write cycle that was initiated in accordance with the write cycle descriptions table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 13 of 32 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. th is part is fully compliant with ieee standard #1149. 1-2001. the tap operates using jedec standard 1.8 v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. test access port test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. this pin may be left unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram on page 15 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) on any register. test data out (tdo) the tdo output pin is used to serially clock data out from the registers. the output is active, depending upon the current state of the tap state machine (see instruction codes on page 19 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and can be performed while the sram is operating. at power up, the tap is reset intern ally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo pins to scan the data in and out of the sram te st circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins, as shown in tap controller block diagram on page 16 . upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is pl aced in a reset state, as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this enables shifting of data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sa mple z instructions can be used to capture the contents of the input and output ring. the boundary scan order on page 20 shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in identification register definitions on page 19 . tap instruction set eight different instructions ar e possible with the three-bit instruction register. all co mbinations are listed in instruction codes on page 19 . three of these instru ctions are listed as reserved and must not be used. the other five instructions are described in this section in detail. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction after it is shift ed in, the tap controller must be moved into the update-ir state.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 14 of 32 idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo pins and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is supplied a test-logic-reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high z state until the next command is supplied during the update ir state. sample/preload sample/preload is an 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the input and output pins is captured in the boundary scan register. you must be aware that the tap controller clock only operates at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or ou tput undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap cont roller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a de sign to stop (or slow) the clock during a sample/preload instructi on. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the k and k captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload places an initial data pattern at the latched parallel outputs of the boundary scan regi ster cells before the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when requir ed, that is, while the data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction drives the preloaded data out through the system output pins. this instruction also connects the boundary scan register for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tristate ieee standard 1149.1 mandates that the tap controller be able to put the output bus into a tristate mode. the boundary scan register has a special bit located at bit #108. when this scan cell, called the ?extest output bus tristate,? is latched into the preload register during the update-dr state in the tap controller, it directly controls the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bi t places the output bus into a high z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the shift-dr state. during update-dr, the value loaded into that shift-register cell latc hes into the preload register. when the extest instruction is entered, this bit directly controls the output q-bus pins. note that this bit is preset high to enable the output when the device is power ed up, and also when the tap controller is in the test-logic-reset state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 15 of 32 tap controller state diagram the state diagram for the tap controller follows. [13] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir note 13. the 0/1 next to each state represents the value at tms at the rising edge of tck.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 16 of 32 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 108 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range parameter [14, 15, 16] description test conditions min max unit v oh1 output high voltage i oh = ?? 2.0 ma 1.4 ? v v oh2 output high voltage i oh = ?? 100 ? a1.6?v v ol1 output low voltage i ol = 2.0 ma ? 0.4 v v ol2 output low voltage i ol = 100 ? a?0.2v v ih input high voltage 0.65 v dd v dd + 0.3 v v il input low voltage ?0.3 0.35 v dd v i x input and output load current gnd ? v i ? v dd ?5 5 ? a notes 14. these characteristics pertain to the tap inputs (tms, tc k, tdi and tdo). parallel load levels are specified in electrical characteristics on page 22 . 15. overshoot: v ih(ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il(ac) > ? 1.5 v (pulse width less than t cyc /2). 16. all voltage referenced to ground.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 17 of 32 tap ac switchi ng characteristics over the operating range parameter [17, 18] description min max unit t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high 20 ? ns t tl tck clock low 20 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns notes 17. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 18. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 18 of 32 tap timing and test conditions figure 3 shows the tap timing and test conditions. [19] figure 3. tap timing and test conditions t tl t th (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9 v 50 ? 1.8 v 0 v all input pulses 0.9 v test clock test mode select tck tms test data in tdi test data out t tcyc t tmsh t tmss t tdis t tdih t tdov t tdox tdo note 19. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 19 of 32 identification regi ster definitions instruction field value description CYRS1543AV18 cyrs1545av18 revision number (31:29) 000 000 version number. cypress device id (28:12) 11010010101010100 11010 010101100100 defines the type of sram. cypress jedec id (11:1) 00000110100 0000011 0100 allows unique identification of sram vendor. id register presence (0) 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 109 instruction codes instruction code description extest 000 captures the input and output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input and output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input a nd output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 20 of 32 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 1j 16p299g575b852j 2 6n 30 11f 58 5a 86 3k 3 7p 31 11g 59 4a 87 3j 47n 329f 605c 882k 5 7r 33 10f 61 4b 89 1k 6 8r 34 11e 62 3a 90 2l 7 8p 35 10e 63 2a 91 3l 8 9r 36 10d 64 1a 92 1m 9 11p 37 9e 65 2b 93 1l 10 10p 38 10c 66 3b 94 3n 11 10n 39 11d 67 1c 95 3m 12 9p 40 9c 68 1b 96 1n 13 10m 41 9d 69 3d 97 2m 14 11n 42 11b 70 3c 98 3p 15 9m 43 11c 71 1d 99 2n 16 9n 44 9b 72 2c 100 2p 17 11l 45 10b 73 3e 101 1p 18 11m 46 11a 74 2d 102 3r 19 9l 47 10a 75 2e 103 4r 20 10l 48 9a 76 1e 104 4p 21 11 k 49 8b 77 2f 105 5p 22 10k 50 7c 78 3f 106 5n 23 9j 51 6c 79 1g 107 5r 24 9k 52 8a 80 1f 108 internal 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1h
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 21 of 32 power up sequence in qdr ii+ sram qdr ii+ srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence apply power and drive doff either high or low (all other inputs can be high or low). ? apply v dd before v ddq . ? apply v ddq before v ref or at the same time as v ref . ? drive doff high. provide stable doff (high), power and clock (k, k ) for 10240 cycles to lock the dll. dll constraints dll uses k clock as its synchronizing input. the input must have low phase jitter, which is specified as t kc var . the dll functions at frequencies down to 120 mhz. if the input clock is unstable and the dll is enabled, then the dll may lock onto an incorrect frequency, causing unstable sram behavior. to avoid this, provide 10240 cycles stable clock to relock to the desired clock frequency. figure 4. power up waveforms k k fix high (tie to v ddq ) v dd /v ddq doff clock start (clock starts after v dd /v ddq is stable) unstable clock > 10240 stable clock start normal operation ~ ~ ~ ~ v dd /v ddq stable (< + 0.1v dc per 50 ns)
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 22 of 32 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c case temperature under power ............... ?55 c to +125 c junction temperature under power .......... ?55 c to +155 c supply voltage on v dd relative to gnd .......?0.5 v to +2.9 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc applied to outputs in high z ........ ?0.5 v to v ddq + 0.3 v dc input voltage [20] ........................... ?0.5 v to v dd + 0.3 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, m. 3015) ............ .............. .............. > 2001 v latch up current .................................................... > 200 ma operating range range case temperature (t c ) v dd [21] v ddq [21] military ?55 c to +125 c 1.8 0.1 v 1.4 v to v dd electrical characteristics over the operating range dc electrical characteristics over the operating range parameter [22] description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 23 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v ol output low voltage note 24 v ddq /2 ? 0.12 ? v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?? 0.1 ma, nominal impedance v ddq ? 0.2 ? v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss ? 0.2 v v ih input high voltage v ref + 0.1 ? v ddq + 0.3 v v il input low voltage ?0.3 ? v ref ? 0.1 v i x input leakage current gnd ? v i ? v ddq ? 20 ? 20 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ? 20 ? 20 ? a v ref input reference voltage [25] typical value = 0.75 v 0.68 0.75 0.95 v i dd [21] v dd operating supply v dd = max, i out = 0 ma, t j = 125 c f = f max = 1/t cyc 250 mhz ( 18) ? ?1225 ma ( 36) ? ? 1225 200 mhz ( 18) ? ?1050 ma ( 36) ? ? 1050 i sb1 automatic power down current max v dd , both ports deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc , t j = 125 c inputs static 250 mhz ( 18) ? ? 510 ma ( 36) ? ? 510 200 mhz ( 18) ? ? 475 ma ( 36) ? ? 475 notes 20. overshoot: v ih(ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il(ac) > ? 1.5 v (pulse width less than t cyc /2). 21. power up: assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 22. all voltage referenced to ground. 23. output are impedance controlled. i oh = ? (v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 24. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 25. v ref(min) = 0.68 v or 0.46 v ddq , whichever is larger, v ref(max) = 0.95 v or 0.54 v ddq , whichever is smaller. 26. the operation current is calculated with concurrent read and write cycles.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 23 of 32 ac electrical characteristics over the operating range parameter [27, 28] description test conditions min typ max unit v ih input high voltage v ref + 0.2 ? ? v v il input low voltage ? ? v ref ? 0.2 v radiation performance parameter test conditions limits unit total dose t a = 25 c, v dd = v ddq = 1.8 v 300 krad rads(si) co60 soft error rate t a = 25 c to 125 c, v dd = v ddq = 1.8 v w/ edac 1.0 10^ -10 upsets/bit-day transient dose rate upset pulse width (fwhm) = 50 ns, x-ray, t c = 25 c, v dd = v ddq = 1.8 v 2.0 10 9 rads(si)/s neutron fluence 1 mev equivalent energy, unbiased t a = 25 ? c 2e14 n/cm 2 latch up immunity t a = 125 c, v dd = v ddq = 1.9 v 110 mevcm 2 /mg capacitance parameter [29] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v dd = 1.8 v, v ddq = 1.5 v 10 pf c clk clock input capacitance 10 pf c o output capacitance 10 pf thermal resistance parameter [29] description test conditions 165-ball ccga package unit ? jc thermal resistance (junction to case) test conditions follow standar d test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 8.9 c/w notes 27. overshoot: v ih(ac) < v ddq + 0.85 v (pulse width less than t cyc /2), undershoot: v il(ac) > ? 1.5 v (pulse width less than t cyc /2). 28. power up: assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd . 29. tested initially and after any design or process change that may affect these parameters.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 24 of 32 ac test loads and waveforms figure 5. ac test loads and waveforms 1.25 v 0.25 v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75 v v ref = 0.75 v [30] 0.75 v under te s t 0.75 v device under te s t output 0.75 v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ? 30. unless otherwise noted, test conditions are based on signal trans ition time of 2 v/ns, timing reference levels of 0.75 v, vr ef = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 5 .
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 25 of 32 switching characteristics over the operating range parameters [31, 32] description 250 mhz 200 mhz unit cypress parameter consortium parameter min max min max t power v dd (typical) to the first access [33] 1?1?ms t cyc t khkh k clock cycle time 4.0 8.4 5.0 8.4 ns t kh t khkl input clock (k/k ) high 1.6 ? 2.0 ? ns t kl t klkh input clock (k/k ) low 1.6 ? 2.0 ? ns t khk h t khk h k clock rise to k clock rise (rising edge to rising edge) 1.8 ? 2.2 ? ns setup times t sa t avkh address setup to k clock rise 0.5 ? 0.6 ? ns t sc t ivkh control setup to k clock rise (rps , wps ) 0.5 ? 0.6 ? ns t scddr t ivkh ddr control setup to clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.5 ? 0.6 ? ns t sd [34] t dvkh d [x:0] setup to clock (k/k ) rise 0.5 ? 0.6 ? ns hold times t ha t khax address hold after k clock rise 0.5 ? 0.6 ? ns t hc t khix control hold after k clock rise (rps , wps ) 0.5 ? 0.6 ? ns t hcddr t khix ddr control hold after clock (k/k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.5 ? 0.6 ? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.5 ? 0.6 ? ns output times t co t chqv k/k clock rise to data valid ? 0.7 ? 0.7 ns t doh t chqx data output hold after output k/k clock rise (active to active) ?0.7 ? ?0.7 ? ns t ccqo t chcqv k/k clock rise to echo clock valid ? 0.7 ? 0.7 ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.7 ? ?0.7 ? ns t cqd t cqhqv echo clock high to data valid ? 0.5 ? 0.5 ns t cqdoh t cqhqx echo clock high to data invalid ?0.30 ? ?0.35 ? ns t cqh t cqhcql output clock (cq/cq ) high [34] 1.55 ? 1.95 ? ns t cqhcq h t cqhcq h cq clock rise to cq clock rise (rising edge to rising edge) [34] 1.55 ? 1.95 ? ns t chz t chqz clock (k/k ) rise to high z (active to high z) [35, 36] ? 0.45 ? 0.45 ns t clz t chqx1 clock (k/k ) rise to low z [35, 36] ?0.45 ? ?0.45 ? ns t qvld t cqhqvld echo clock high to qvld valid [37] ?0.5 0.5 ?0.5 0.5 ns dll timing t kc var t kc var clock phase jitter ? 0.2 ? 0.2 ns t kc lock t kc lock dll lock time (k) 10240 ? 10240 ? cycles t kc reset t kc reset k static to dll reset 30 ? 30 ? ns notes 31. unless otherwise noted, test conditions are based on signal transiti on time of 2 v/ns, timing reference levels of 0.75 v, vr ef = 0.75 v, rq = 250 ? , v ddq = 1.5 v, input pulse levels of 0.25 v to 1.25 v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of figure 5 on page 24 . 32. when a part with a maximum frequency above 167 mhz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 33. this part has a voltage regulator internally; t power is the time that the power must be supplied above v dd(minimum) initially before a read or write operation can be initiated. 34. these parameters are extrapolated from the input timing parameters (t khk h ? 250 ps, where 250 ps is the internal jitter. an input jitter of 200 ps (t kc var ) is already included in the t khk h ). these parameters are only guaranteed by design and are not tested in production 35. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of figure 5 on page 24 . transition is measured 100 mv from steady-state voltage. 36. at any voltage and temperature t chz is less than t clz and t chz less than t co . 37. t qvld spec is applicable for both rising and falling edges of qvld signal.
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 26 of 32 switching waveforms figure 6. read/write/deselect sequence [38, 39, 40] t kh t kl t cyc t khkh nop read nop write read write 1 23 4 5 6 7 8 t t t t sa ha sc hc t hd t sc t hc a0 a1 a2 a3 t t sd hd t sd d11 d10 d12 d13 d30 d31 d32 d33 d a wps rps k k dont care undefined cq cq t cqoh ccqo t t cqoh ccqo t t qvld qvld t qvld (read latency = 2.0 cycles) clz t t co t doh t cqdoh cqd t t chz q00 q01 q20 q02 q21 q03 q22 q23 t cqh t cqhcqh q notes 38. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, that is, a0 + 1. 39. outputs are disabled (high z) one clock cycle after a nop. 40. in this example, if address a2 = a1, then data q20 = d10, q21 = d11, q22 = d12, and q23 = d13. write data is forwarded immed iately as read results. this note applies to figure 6 .
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 27 of 32 ordering code definitions ordering information the following table contains only the parts th at are currently available. if you do not see what you are looking for ( 18 opti on), contact your local sales representative. for more information, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cyp ress.com/products . cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representat ives and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (mhz) ordering code description package diagram package type operating range 250 CYRS1543AV18-250gcmb 72m qdr ii+, 18, burst of 4 001-58969 165-ball ccga (21 25 2.83 mm) military 250 cyrs1545av18-250gcmb 72m qdr ii+, 36, burst of 4 001-58969 165-ball ccga (21 25 2.83 mm) military 250 cypt1543av18-250gcmb 72m qdr ii+, 18, burst of 4, prototype 001-58969 165-ball ccga (21 25 2.83 mm) military 250 cypt1545av18-250gcmb 72m qdr ii+, 36, burst of 4, prototype 001-58969 165-ball ccga (21 25 2.83 mm) military 250 5962f1120102qxa 72m qdr ii+, 18, burst of 4, dlam part 001-58969 165-ball ccga (21 25 2.83 mm) military 250 5962f1120202qxa 72m qdr ii+, 36, burst of 4, dlam part 001-58969 165-ball ccga (21 25 2.83 mm) military 250 CYRS1543AV18-1xwi 72m qdr ii+ die n/a military burn-in thermal rating: m = military package type: 165-ball ccga speed grade: 250 mhz core voltage: 1.8 v die revision part number identifier: d ensity, organization, burst 154x = 1543 or 1545 marketing code: xx = rs or pt rs = radstop, pt = prototype company id: cy = cypress xx cy 154x a - 250 gc v18 mb
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 28 of 32 package diagram figure 7. 165-ball ceramic column grid array (ccga) (21 25 mm) package outline, 001-58969 001-58969 *c
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 29 of 32 acronyms document conventions units of measure acronym description bws byte write select ccga ceramic column grid array ded double error detection dll delay lock loop ddr double data rate dscc defense supply center columbus edac error detection and correction hstl high speed transceiver logic i/o input/output jtag joint test action group lsb least significant bit lsbu logical single-bit upsets lmbu logical multi-bit upsets msb most significant bit pda percent defect allowable pind particle impact noise detection pda percent defective allowable qdr quad data rate rps read port select sec single error correction sel single event latch up sram static random access memory tap test access port tck test clock tdi test data in tdo test data out tms test mode select wps write port select symbol unit of measure c degree celsius krad kiloradian mhz megahertz a microampere f microfarad s microsecond ma milliampere mm millimeter ms millisecond mv millivolt n/cm 2 neutron particles fluence per cm 2 area ns nanosecond nm nanometer ? ohm % percent pf picofarad ps picosecond rads(si) unit of absorbed radi ation energy from ionizing radiation per kg of material. (1 rad(si)) = 10 mgy = 10 ? 2 j/kg vvolt wwatt
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 30 of 32 glossary total dose permanent device damage due to ions over device life heavy ion instantaneous device latch up due to single ion let linear energy transfer (measured in mevcm 2 ) krad unit of measurement to determine dev ice life in radiation environments. neutron permanent device damage due to energetic neutrons or protons prompt dose data loss of permanent device damage due to x-rays and gamma rays < 20 ns 165-ball ceramic column grid array hermetic ceramic 165-co lumn package. columns attached by six sigma radstop technology cypress's patented rad hard design methodology dlam defense logistics agency land and maritime lsbu logical single bit upset. single bits in a single correction word are in error. lmbu logical multi bit upset. multiple bits in a single correction word are in error. group a general electrical testing group b mechanical - dimensions, bond strength, solvents, die shear, solderability, lead integrity, seal, acceleration group c life test - 1000 hours at 125 ? c group d package related mechanical tests - shock, vibration, accel, sa lt, seal, lead finish adhesion, lid torque, thermal shock, moisture resistance group e radiation testing
CYRS1543AV18 cyrs1545av18 document number: 001-60007 rev. *h page 31 of 32 document history page document title: CYRS1543AV18/cyrs1545av18, 72-mbit qdr ? ii+ sram four-word burst ar chitecture with radstop? technology document number: 001-60007 rev. ecn no. submission date orig. of change description of change ** 2940931 05/31/2010 hrp new data sheet. *a 3016545 08/26/2010 hrp changed part numbers fr om cyrs1513av18, cyrs1515av18 to reflect change to qdr ii+ die. updated switching characteristics (updated minimum and maximum values for setup time, hold time parameters, and updated minimum and maximum values for t co parameter under output time parameter). updated package diagram . added units of measure . *b 3281455 06/13/2011 hrp changed status from advanced to final. updated configurations (corrected typo). updated selection guide . updated dc electrical characteristics (maximum current limit values for the parameters idd and isb1 based on device characterization). updated radiation performance (limits of radiation data based on rha qualification). updated thermal resistance . updated switching characteristics (minimum and maximum timing values for the parameters t co , t doh , t ccqo , t cqoh based on device characterization. updated ordering information (removed 18 option from ordering table). updated package diagram . changed dll lockup cycles from 2048 to 10240 throughout document. updated in new template. *c 3471321 12/21/2011 hrp updated identification register definitions (replaced the value of cypress device id (28:12) from 11010011011010100 to 11010010101010100 for CYRS1543AV18 and replaced the value of cypress device id (28:12) from 11010011011100100 to 11010010101100100 for cyrs1545av18). *d 3524961 02/14/2012 hrp updated prototyping under radiation performance (added two devices). updated selection guide (removed 200 mhz option). updated application example . updated truth table . updated maximum ratings . updated operating range . updated radiation performance . updated capacitance . updated thermal resistance . updated switching characteristics . *e 3537277 02/29/2012 hrp updated radiation data under radiation performance . updated ordering information (added the part numbers CYRS1543AV18-250gcmb, cypt1543av18-250gcmb, cypt1545av18-250gcmb, 5962f1120203vxa and CYRS1543AV18-1xwi). *f 3617759 05/15/2012 hrp updated ordering information (added part 5962f1120103vxa). updated glossary . *g 3640834 06/08/2012 hrp updated radiation performance (updated prototyping ). renamed the section class v flow as manufacturing flow . updated glossary . *h 3857750 01/04/2013 hrp updated ordering information (updated part numbers).
document number: 001-60007 rev. *h revised january 4, 2013 page 32 of 32 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oducts and company names mentioned in this document may be the trademarks of their respective holders. CYRS1543AV18 cyrs1545av18 ? cypress semiconductor corporation, 2010-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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